The present invention relates to integrated circuits, and more particularly, to circuits for driving power devices including voltage level shifters.
Power conversion control circuits often use voltage level shifter circuits to translate input logic voltage level signals operating at low voltages (e.g. xe2x80x9clow sidexe2x80x9d at 5 to 12 volts) to output signals at higher voltage levels (e.g. xe2x80x9cHigh sidexe2x80x9d at 100-112V). For example, automotive, electronic data processing, and industrial control applications require high voltage level shifter circuits to drive various peripheral devices. Such circuits are often implemented in application specific integrated circuits (ASICs) or as independently packaged circuits. Voltage level shifter circuits are usually implemented with logic level devices, fabricated using metal oxide semiconductor field effect transistors (MOSFETS).
Voltage level shifter circuits normally receive an input signal and output an output signal at a different voltage than the input signal. Ideally, voltage level shifter circuits should draw no DC current from the power supplies used to determine the desired output voltages. The output voltages attainable are a function of the power supplies to the shifter circuit and the capabilities of the devices used to build the circuit.
As mentioned, voltage level shifter circuits translate a logic level input signal to signals at high voltage levels. This is a common need in half and full bridge drivers. Conventional approaches send a continuous or pulsed current signal to one high side node to signal a logic xe2x80x9c0xe2x80x9d state, or a continuous or pulsed current signal to a second high side node to signal a logic xe2x80x9c1xe2x80x9d state. When the current signal flows, it flows from the high side voltages to the low side voltages, which can be many hundreds of volts differential, limited only by the breakdown voltage of the transmitting/receiving devices. Accordingly, when this current flows across these large voltages, relatively high power dissipation occurs.
In view of the foregoing background, it is therefore an object of the invention to provide a circuit and method for translating a logic level input signal to signals at high voltage levels to drive a power device, such as a power MOSFET, while minimizing the power consumption.
This and other objects, features and advantages in accordance with the present invention are provided by a high side gate driver. The high side gate drive includes a high side gate driver logic input, a high side gate driver output, a latch connected between the high side gate driver logic input and the high side gate driver output, and a control circuit receiving an output of the latch and controlling signals from the high side gate driver logic input to the latch based upon the output of the latch.
Preferably, the high side gate driver further comprises first and second level shifting signal paths connecting the high side gate driver logic input and the latch. A first switch is in the first level shifting path between the high side gate driver logic input and the latch controlled by the output of the latch, and a second switch is in the second level shifting path between the high side gate driver logic input and the latch controlled by an inverted output of the latch. The first and second switches may comprise P-channel pass transistors. Also, the high side gate driver may include a high side floating voltage supply, and respective loads, such as resistors, connecting the first and second level shifting signal paths to the high side floating voltage supply.
The high side gate driver may also comprise a first current source in the first level shifting path controlled by the high side gate driver logic input, and a second current source, out of phase with the first current source, in the second level shifting path controlled by the high side gate driver logic input. As such, the first and second current sources may comprise respective out of phase NMOS pass transistors controlled by the high side gate driver logic input and connected to a reference voltage supply. Additionally, the latch may be an active low SR latch.
Objects, features and advantages in accordance with the present invention are also provided by a method for driving the power device including latching a high side gate driver logic input signal with a latch, outputting a high side gate driver output signal based upon the latched high side gate driver logic input signal, and controlling the high side gate driver logic input signal based upon the high side gate driver output signal to minimize power consumption. Controlling the high side gate driver logic input signal preferably comprises controlling first and second level shifting signal paths connecting a high side gate driver logic input and the latch. Again, switches, such as P-channel pass transistors, in the level shifting paths between the high side gate driver logic input and the latch are controlled by an output of the latch.
Controlling the first and second level shifting signal paths may further include connecting respective loads, such as resistors, between the first and second level shifting signal paths and a high side floating voltage supply, and providing current sources, such as respective out of phase NMOS pass transistors, in the level shifting paths controlled by the high side gate driver logic input.